CS441 - Architecture - 2007
|Meeting time: TR 9:45-11:15
Room 106 Chapman Building
University of Alaska Fairbanks
|UAF CS F441-F01
3.0 Credits, Fall 2007
Prerequisites: CS 321 (OS), EE 341
|Instructor: Dr. O. Lawlor
Office: 210C Chapman
Hours: 11:15-noon TR, by appointment, or just drop by!
- Final Exam, Project 2, and overall course grades are posted
on NetRun. I have chosen not to use +/- grades. Thanks, guys--this has been a
- Final exam thoughts:
- Multi-core's major costs include software, fabrication cost ($$$), bus bandwidth/cache contention, heat, software, design time, reliability, communication latency, software, software, and of course software.
- For the MIPS-assembly dependency question:
A.) li $2, 123
B.) li $3, 223
C.) add $4, $2, $3
D.) li $2, 456
E.) li $3, 556
There are six dependencies here:
C RAR A. C RAR B.
D WAR C. E WAR C. (these can be renamed away)
D WAW A. E WAW A. (these can also be renamed away)
(My "HINT" for this problem didn't help, because nobody else seemed to merge labels like I did.)
- The Project
2 code and README file were turned in on
Blackboard by midnight Tuesday, December 18 (same day as the final
- The HW6 "answer key" (my parallel implementation) is on the powerwall in
Project 1 Presentation Schedule
- Here's the VHDL-written DLX CPU Simulator we looked at in class (or browse the directory). It was written back in 1993 by Peter J. Ashenden. DLX is a subset of MIPS.
- NetRun lets you run code
right from your web browser. Anybody with a UAF email address can get a password online. See
Send me bug reports!
- Lecture Notes:
Course Review for Final Exam
OpenMP: Threaded Programming for Mortals
Parallel Performance Theory
Powerwall Accounts & Parallelism
MPI and Scientific Simulation
Intel Threading Building Blocks
Parallel Programming Survey
Course Review For the Midterm
Etching Printed Circuit Boards the Gootee Way
Superscalar, Out-of-Order, and Hazards
MIPS: Machine without Interlocking Pipeline Stages
Whole-CPU Simulation and Pipelining
SPICE, VHDL, and Software for Hardware Design
Digital vs. Analog Circuits: Not a Binary Choice!
- Course syllabus
includes dates to remember, the grading policy, and a course outline.
Tuesday, October 9, 2007
||Thursday, October 11
|Tuesday, October 16
|Thursday, October 18
O. Lawlor, firstname.lastname@example.org
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