# SPICE, VHDL, and Software for Hardware Design

CS 441 Lecture, Dr. Lawlor

So, you want to build some hardware.  Back in the day (that is, in 1985), you would start with a pile of logic chips, each with as many as four logic gates on it, and solder together a big ball of wires (known as "rat's nest" circuit layout).

Unfortunately, this doesn't scale.  Past a certain complexity (say, a thousand pins), you basically can't fabricate a working circuit by hand in a reasonable length of time.  Figuring out how and where to route the wires, and actually routing the wires, becomes virtually impossible.

So since the 1960's, people have turned to computers to design the circuits used for computers, which is to say Computer Aided Circuit Design or the modern term Electronic Design Automation.  (You know that Terminator quote "... at 2am SkyNet began learning at a geometric rate"?  Yeah, that's a restatement of Moore's Law.)

## SPICE Analog Circuit Simulation

For analog circuits, the 1970's Fortran program SPICE simulates analog circuits.  It can simulate the dynamic time-dependent behavior of the circuit (transient analysis), steady-state current flow (static analysis), or even a high-frequency view (AC analysis).  Basically you write a simple line-oriented ASCII input file, run SPICE on it, and stare at the output.

Here's an example machine-readable SPICE input file, and my human-readable description of each line.  Here's some more formal documentation
 `Simple Voltage Divider Circuit* By Dr. Orion Sky LawlorVcc 1 0 DC 5vRa 1 2 1KRb 2 0 1K.tran 0.2ms 10ms.print tran v(2)` `simulation titlecomment line (can occur anywhere)5V DC voltage source at node 11K resistor hooked up to 5V source (at node 1)1K resistor hooked up to ground (node 0)"transient analysis" running for 10msprint the voltage at node 2, between the resistors`

The first line of your SPICE input file is the *title* of the simulation.  It's free-form text.

The middle of your SPICE file is a list of components, and how they connect via "nodes" to other components.  Nodes are just integers indicating a place where wires meet.  Node zero is always ground.  A component names' first letter always determines the type of component--for example, "Rfoo" is a Resistor, while "Vfoo" is a voltage source, or "Cfoo" a capacitor.  (see the complete component list)

The last lines of your SPICE file say what sort of analysis and output you want.  Here, I'm asking for a transient analysis at 0.2ms minimum time resolution, running for a total of 10.0ms.  I'm also asking SPICE to print the voltage at node 2, which is a constant 2.5vdc.

Here's a circuit with slightly more interesting-looking output.  It's a resistor-capacitor circuit, driven by a pulsed voltage source.  The format of the PULSE(...) statement is low_voltage  high_voltage  start_delay  rise_time  fall_time  high_time  period.
`Simple Capacitor-Pump Circuit*  By Dr. Orion Sky LawlorVcc 1 0 PULSE(0v 5v 2ms 1us 1us 1ms 2ms)Ra 1 2 1KCb 2 0 0.3uF.tran  0.2ms  10ms.print tran v(2)`

Try it!

## VHDL Digital Circuit Design

There are several different languages out there for digital circuit design.  VHDL (.vhd or .vhdl), Very High-level hardware Design  Language, is probably the biggest digital circuit description language (the only other major language is Verilog (.v)) .  VHDL's syntax derives from Pascal by way of Ada, and like those languages it's got a lot of "housekeeping" syntax.  Here's hello world:
`use std.textio.all;entity foo isend foo;architecture arch of foo isbegin        process                variable L : line;        begin                write(L, string'("a big old hello world!"));                writeline(output, L);                wait;        end process;end arch;`

Notice that there's no sign of a *circuit* here!  Indeed, you can run your VHDL in a huge variety of ways.  You can simulate VHDL on the CPU using a VHDL-to-executable-code translator like ghdl or use any of a variety of commercial simulators.  Or you can use a VHDL-to-FPGA programming tool (like this FPGA IDE from Xilinx) to make the VHDL code run directly on an FPGA.  Or you can "tape-out" a VHDL design to actual silicon ASIC, a custom chip that runs your code directly.  Custom silicon prices start at about \$20,000 from MOSIS, for 40 tiny chips.

Stuff inside a "process ... begin .. end process" basically looks like  sequential C-like code.  But there's a twist--everything between every entity's process begin/end pairs executes repeatedly, over and over again.   Try the above code without the "wait;", and it'll keep printing hello!  "wait;" actually means "wait forever here", which in the simulator means "exit".

But it's even weirder with multiple process statements (which is very common), or for stuff outside a process; everything else actually executes concurrently!  This is how real hardware works--all your logic, muxes, registers, gates, and so on just runs all the time.  Sequential C/C++/Java/C#/VB programmers aren't at all used to this.

Here's a VHDL program with three separate things happening at once:
`use std.textio.all;entity foo is end foo;architecture arch of foo is  signal BOB: bit;  -- BOB and TED are both bits.  signal TED: bit;begin  process  -- Drives BOB low, then high.  begin    BOB <= '0';  wait for 1000 ns;    BOB <= '1';  wait;  end process;  TED <= BOB; -- Always copies BOB's value into TED  process -- Waits for BOB, then prints TED    variable L : line;  begin    wait until BOB = '1';    wait for 1 ns;  -- Time for TED to catch up (important!)    write(L, TED);    writeline(output, L);    wait;  end process;end arch;`