Storage Circuitry

CS 441 Lecture, Dr. Lawlor

Dynamic RAM, or "DRAM", is implemented as an array of bits, each bit containing a capacitor (to store one bit) and a transistor (to write or read off the capacitor's charge).  The capacitors slowly bleed off charge, so they need to be periodically refreshed.  A typical modern silicon implementation pushes the capacitors into 3D, either in a deep trench (DT) or stacked-capacitor (SC) layout.

Modern DRAM is sold on the basis of the motherboard's memory bus speed, plus a set of memory timings in clock cycles.  They've slowly cranked up this speed over the years, mostly by doing multiple data transfers per memory clock cycle (e.g., 2 transfers per clock with "Double Data Rate" DDR, 4 transfers and 2 commands per clock with DDR2, etc).  The latest modification is "DDR3", which does a ridiculous 8 transfers and 4 commands per 200MHz memory clock.  Bandwidth is linear in clockrate, but latency doesn't quite decrease linearly with clockrate, because at the faster clockrates, the latency measured in clock cycles is actually increasing:

Memory timing examples (CAS latency only)
Type Data rate Bit time Command rate Cycle time CL First word Fourth word Eighth word
PC100 100 MT/s  10 ns 100 MHz  10 ns 2 20 ns 50 ns 90 ns
PC133 133 MT/s  7.5 ns 133 MHz  7.5 ns 3 22.5 ns 45 ns 75 ns
DDR-333 333 MT/s  3 ns 166 MHz  6 ns 2.5 15 ns 24 ns 36 ns
DDR-400 400 MT/s  2.5 ns 200 MHz  5 ns 3 15 ns 22.5 ns 32.5 ns
2.5 12.5 ns 20 ns 30 ns
2 10 ns 17.5 ns 27.5 ns
DDR2-667 667 MT/s  1.5 ns 333 MHz  3 ns 5 15 ns 19.5 ns 25.5 ns
DDR2-800 800 MT/s  1.25 ns 400 MHz  2.5 ns 6 15 ns 18.75 ns 23.75 ns
5 12.5 ns 16.25 ns 21.25 ns
DDR3-1066 1066 MT/s  0.9375 ns 533 MHz  1.875 ns 7 13.13 ns 15.95 ns 19.7 ns
DDR3-1333 1333 MT/s  0.75 ns 666 MHz  1.5 ns 9 13.5 ns 15.75 ns 18.75 ns
6  9 ns 11.25 ns 14.25 ns
DDR3-1375 1375 MT/s  0.73 ns 687 MHz  1.5 ns 5  7.27 ns  9.45 ns 12.36 ns
DDR3-1600 1600 MT/s  0.625 ns 800 MHz  1.25 ns 9 11.25 ns 13.125 ns 15.625 ns
8 10 ns 11.875 ns 14.375 ns
7  8.75 ns 10.625 ns 13.125 ns
(Table from Wikipedia CAS latency article, Creative Commons license)

SRAM

Static RAM (not to be confused with SDRAM, Synchronous Dynamic RAM) is *not* dynamic; no capacitors.  Because there's no analog circuitry, it's substantially faster: access can be sub nanosecond.  Because it takes six transistors per bit, it costs more money, area, and power than DRAM.

Flash Memory

Flash Memory is developing as an interesting intermediate between hard drives and RAM.  It's nearly as big as hard drives (dozens of gigabytes), but nearly as fast as RAM (hundreds of megabytes per second). 

Cameras

Curiously, although modern DRAM can function as a camera, the CCD device inside a modern camera actually evolved from memory (the CCD started out as an electronic version of magnetic bubble memory, also built at Bell labs).