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# Branch Instructions

## In MAL, conditional branch instructions are available for all possible equality and inequality relations for testing two registers against each other or a single register against zero. In TAL, only beq and bne are provided in the two register form. The relational tests bgez, blez, bgtz, and bltz are provided only in the single register form. All other MAL forms can be synthesized by: Reversing the sense of the comparison; Subtracting the values to be compared and comparing the result against zero. For example, the MAL instruction: ` blt \$11, \$12, loop` can be synthesized from the TAL instructions: ``` sub \$1, \$11, \$12 bltz \$1, repeat``` In this example, register \$1 (\$at) is used as a temporary register by the assembler to hold an intermediate result required for the synthesis of the MAL instruction. The synthesis of the MAL blt will not work correctly if the difference between the registers \$11 and \$12 overflows. This is possible if \$11 contains a very large positive number and \$12 contains a large negative number, or vice versa. If the difference results in overflow, the sub instruction will produce an exception which interrupts the execution of the program. The subu instruction could be used instead of sub to avoid an exception, but unsigned subtraction produces incorrect numerical results for negative integers and may lead to an incorrect branch decision. Note that the original MAL instruction is well-defined and should execute correctly for all possible register values. The TAL slt (set less than) instruction is designed specifically to compare the 2's complement values in two registers without overflow. The result of the instruction is to set the destination register to either 1 (true) or 0 (false) according to the result of the comparison. The MAL blt instruction can be correctly synthesized using slt as: ``` slt \$1, \$11, \$12 bne \$1, \$0, loop``` If register \$11 is less than \$12, register \$1 is set to 1 and otherwise to 0. The TAL bne instruction uses register \$0 to simulate the MAL bnez instruction. There is also a slti (set less than immediate) instruction which compares a sign-extended immediate constant with the value in a register and sets the destination register in the same manner as for slt. The TAL branch instructions are: Notes: , , are general registers. specifies an immediate field within the instruction. Superscripts indicate repetitions of a binary value. Subscripts indicate bit positions (Little-Endian) of sub-field. Square brackets ([ ]) indicate "contents of." Note that the conditional branch instructions reset the program counter (PC) when the branch test is satisfied. All branch instructions contain the target address as an immediate constant. The constant equals the difference between the target address and the address of the instruction immediately following the branch instruction. The constant is the relative address of the target in relation to the branch instruction represented as a 2's complement integer. Since instructions must begin on word boundaries, the branch instructions set the least significant two bits of the relative address to 0. The constant itself is 16 bits in length. Thus, branches are limited to relative addresses which can be expressed in 18 bits, which is a range of 128K bytes, or 32K instructions. Branch instructions are used mainly to create loops, which are usually smaller than 32K instructions. The great advantage of PC relative addresses is that branch instructions work correctly no matter where they are loaded into memory, as long as the branch and the target address remain in the same relative positions. This allows blocks of machine code to be relocated in memory without recalculating the addresses stored in the branch instructions. All TAL branch instructions involve a test to determine whether a branch is taken. Unconditional branches are called jump instructions in TAL. The MAL unconditional branch, b, is equivalent to the TAL j (jump) instruction. In the MAL jump instruction, j, the target address can be either a label or the contents of a register. TAL provides separate instructions for these cases. The TAL j instruction requires that the address be a label. The jr (jump register) instruction is used when the address is contained in a register. The jr instruction is identical in MAL and TAL. Similarly, the MAL jal instruction allows the target address to be specified as either a label or the contents of a register. The TAL jal instruction allows only a label for the address. The jalr instruction, which is identical in MAL and TAL, must be used to specify a jump address contained in a register in TAL.

Next: Load/Store Instructions Up: TAL Previous: Arithmetic and Logical Instructions

CS 301 Class Account
Mon Dec 1 23:34:28 AST 1997