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T3D Architecture

The CRAY T3D is a parallel computer built around DEC Alpha RISC processors. The T3D is available in sizes ranging from 32 to 2048 processors (PEs). The memory architecture is physically distributed and logically shared (globally addressable). The name of the machine is derived from the the processor interconnect network, which is a three-dimensional torus [3].

The T3D requires a frontend host computer system to provide support for applications running on the T3D. All applications written for the T3D are compiled on the host system in MPP Fortran, Fortran 90, C or C++. The host system also provides job scheduling and I/O control for the T3D. Host systems include the CRAY Y-MP and CRAY C90 series computers. The Arctic Region Supercomputing Center (ARSC) operates a T3D with 128 PEs running at 150 Mhz and providing a peak speed of 19.2 GFLOPS. Each PE contains 8 MW (64 MB) of local memory, which provides 1 GW (8 GB) of globally addressable physical memory. The host machine for the ARSC T3D is a CRAY Y-MP M98 with 8 CPUS and 1 GW (8 GB) of memory.

The T3D processors are dynamically divided into partitions which appear to the user as logically separate dedicated machines, allowing multiple users to share the T3D. The number of processors allocated in a partition must be a power of 2. T3D jobs are initiated on the host system and may be run interactively or using batch queues. To run a T3D job, the host runs a process called mppexec which spawns an agent process on the host for each PE in the partition and then loads the T3D executables. These agents provide the control and I/O interface for the T3D through the frontend host.



Mitch Roth
Tue Aug 6 09:57:21 ADT 1996