Instruction Cycle

To execute the SAL instruction:

add A, B, C

1. Fetch instruction (add) from memory address PC.
2. Increment PC to address of next instruction.
3. Decode the instruction and operands.
4. Load the operands B and C from memory.
5. Execute the add operation.
6. Store the result into memory location A.

Execution Time

Suppose each memory access (fetch, load, store) requires 10 clock cycles and that the PC update, instruction decode, and execution each require 1 clock cycle. The total number of cycles to execute the add instruction is:

10+1+1+10+10+1+10 = 43 cycles/instruction.

A CPU running at 100 Mhz (100,000,000 cycles/sec) can execute add instructions at a rate of 100,000,000/43 = 2,325,581 instructions/sec, or ~2.3 Mips (million instructions/sec).

By using fixed length instructions, RISC CPUs can combine steps 1 and 2 of the instruction cycle into a single step in which the PC update occurs simultaneously with the instruction fetch and does not require an extra clock cycle.

CISC CPUs with variable length instructions must fetch and decode an instruction before the PC can be incremented.