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Architecture Research: ARM Architecture

Mariya Shapran


What is ARM architecture? The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture


Typical RISC architecture features present in ARM architecture:

-          a large uniform register file

-          a load/store architecture (in this case, data-processing operations only operated on registered contents)

-          simple addressing modes, with all load/store addressed determined from register contents and instruction fields only


ARM architecture specifics that according to the ARM Architecture Reference Manual enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area:

-          instruction that combine a shift with an arithmetic or logical operation

-          auto-increment and auto-decrement addressing modes to optimize program loops

-          load and store multiple instructions to maximize data throughput

-          conditional execution of almost all instructions to maximize execution throughput



ARM is a 32-bit reduced instruction set computer instruction set architecture. ARM abbreviation was known as Advanced RISC Machine, as well as Acorn RISC Machine.

Due to the suitability for low power applications ARM Processors became quite dominant in the mobile industry and embedded electronics market.

At this time, we can find ARM processors anywhere from mobile phones, to PDA, calculators, MP3 players, routers and other small electronics.


Basic Facts about ARM Processor:

-  ARM Processor(s) was designed by ARM Holidings

- 32-bits

- first processor was introduced in 1983

- design RISC

- Type Register-Register

- Encoding is Fixed

- Branching is Condition Code

- Endianness Bi (Little as default)

- Registers – 16



Technically, ARM has 31 general-purpose 32-bit registers, but at any one time, 16 of these registers are visible.

Remaining registers utilized to speed up exception processing. All registers specified in ARM instructions can address any of the 16 visible registers.


General-purpose registers:

-          Unbanked registers – R0 to R7    (each of them refers to the same 32-bit physical register in all processor modes)

-          Banked registers – R8 to R14 (


Three of the 16 visible registers have special roles

-          Stack Pointer (R13) – used by the PUSH and POP instructions in T variants, and by SRWS and RFE instructions from ARMv6

-          Link Register (R14) – holds the address of the next instruction after a Branch and Link (BL and BLX) instructions used to make a subroutine call;

-          Program Counter (R15) – can be used in most instructions as a pointer to the instructions which is two instructions after instruction being executed.

Remaining 13 register have no special HW purpose. Their uses are defined purely by software.


ARM Instruction Set:

There are six classes of instructions:

-          Branch Instructions

-          Data-Processing instructions

-          Status register transfer instructions

-          Load and store instructions

-          Coprocessor instructions

-          Exception-generating instructions



ARM memory Model:

ARM architecture uses a single, flat address space of 232  8-bit bytes.

Such architecture provides facilities for:
- faulting unaligned memory accesses

-          restricting access by applications to specified areas of memory

-          translating virtual addresses provided by executing instructions into physical address

-          altering the interpretation of word and halfword data between big-endian and little-endian

-          optionally preventing out-of-order access to memory

-          controlling caches

-          synchronizing access to shared memory by multiple processors


Data Types:

ARM Processors support following data types:

Byte                 8 bits

Halfword            16 bits

Word                32 bits


ARM Architecture Supports 7 processor modes:

User                 usr        0b10000            Normal program execution mode (

FIQ                   fiq         0b10001            Supports a high-speed data transfer or channel process (exception and privileged mode)

IRQ                   irq         0b10010            Used for general-purpose interrupt handling (exception and privileged mode)

Supervisor         svc       0b10011            A protected mode for the operating system (exception and privileged mode)

Abort                abt        0b10111            Implements virtual memory and/or memory protection (exception and privileged mode)

Undefined          und       0b11011            supports software emulation of HW coprocessors (exception and privileged mode)

System             sys       0b11111            Runs privileged operating system tasks (privileged mode)


Format of the CPSR and the SPSRs:



Fig 1: ARM Architecture Reference Manual



Variety of ARM Processors and their application


Fig 2: provided by ARM.com


Recent Developments:

In January 2011, ARM and IBM made an announcement about agreement between them to extend collaboration on advanced semiconductor technologies.

Focus will be on developing next generation of mobile products with optimized performance and of course, greater efficiency in power.





http://www.nanowerk.com/news/newsid=19744.php - Industry latest developments

ARM Architecture Reference Manual

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition Errata markup