Building Logic Gates from Silicon

CS 441 Lecture, Dr. Lawlor

(From last class: this is the most beautiful free-air arcing I've ever seen.  It's just a spark, but on a massive scale.  It rises because hot air rises.)

Semiconductors and the "Depletion Region"

Silicon doesn't conduct well: it's not a conductor like copper, or an insulator like plastic, it's a semiconductor.  Silicon doped with a few extra electrons ("n-type") conducts current because the electrons move.  Silicon doped with a few electron holes ("p-type") conducts current because the holes move.  Silicon without extra electrons or holes is a reasonably good insulator.

If you put p-type silicon next to n-type silicon, and apply a charge across the two types, something very interesting happens: the electrons and holes can move in opposite directions.  With the charge in one direction, both electrons and holes leave the boundary making an insulating "depletion region".  If you put the charge the other direction, the electrons and holes converge on the boundary and cancel each other out, conducting current.  This is a semiconductor diode!

Modern transistors are FET transistors: you charge up a small channel called the "gate", and it opens the depletion region allowing current to conduct between two terminals. 
MOSFET, showing big insulating depletion region

In an "n-channel FET", the you attract electrons to the gate with a positive voltage to narrow the depletion region and allow it to conduct.    In a "p-channel FET", you open the gate with a negative voltage.  I like Wikipedia's pictures for these: n-channel is an active-high positive logic input, and p-channel is an active-low inverting input with an inverting circle.

Silicon FET Transistors to Logic Gates

You can build logic gates from FET transistors quite easily in a "totem pole" configuration.  Here's an inverter:
CMOS inverter image

When A is positive, it turns off the high gate, disconnecting Q from positive voltage (Vdd); and turns on the low gate, connecting Q to the negative voltage (Vss): A positive makes Q negative.  When A is negative, it turns on the high gate and off the low gate, connecting Q to positive voltage and disconnecting negative voltage; A negative makes Q positive.

Here's a NAND gate built from FET transistors, and the corresponding silicon implementation:
CMOS FET NAND gate   Silicon implementation of FET gates

It's surprisingly easy to build all the logic gates with FET transistors!

Until 2017, I showed an AND gate on this page, but on real chips designers tend to use NAND gates instead of AND gates. They do this because NAND happens to need the active-low PMOS transistors on the high side, and the active-high NMOS transistors on the low side--this makes the transistor gate voltages large, which rapidly and efficiently switches the transistor completely on (called saturation mode). By contrast, if you try to put an active-high NMOS transistor on the high side, all the pins of the transistor are high, so the transistor doesn't really turn on. This has a bad enough impact on the gate's analog characteristics that when real chip designers need to build an AND gate, they just use a NAND followed by an inverter!

Why do you care?

There's an annoying phenomenon called "latchup" where the current going through a logic gate can leak away and keep the gate open.  The affected circuit is then stuck in this state until you turn the power off.

I encountered a latchup error in the memory subsystem of my GPU this summer: the machine had been running fine for weeks, when suddenly it started giving bad output from programs.  Initially, of course, you suspect the program is at fault, but going back to a known-good version it still failed.  A memory tester program revealed tons of memory errors, so I suspected the graphics card driver (a new beta version) had corrupted itself, so I rebooted the machine.  This was a warm boot, the only kind you can perform over the network (remember that it's summertime, so I'm not in my office).  It didn't fix the problem--the memory errors were still there just like before the reboot.  At this point, I realized: it's not software, it's hardware!  The next trip into my office, I powered the machine off, waited a few seconds (to clear the latchup), and the powered it back on.  Problem solved.

In April 2010 a similar bug affected Galaxy 15, a satellite in geosynchronous orbit that stopped responding to commands.  Over a period of months, it drifted off course while still broadcasting at full blast.  Eventually, the satellite lost orientation control, so the solar panels no longer faced the sun, drained its own batteries, and rebooted itself in late December.  It now seems fine, possibly the victim of a cosmic ray induced latchup (a known hazard for space computers).