CS 441 - Computer Architecture

Meeting time: TR 9:45-11:15am
Room 106 Chapman Building
University of Alaska Fairbanks

UAF CS F441-F01
3.0 Credits, Fall 2008
Prerequisites: CS 321 (OS), EE 341

Instructor: Dr. O. Lawlor
ffosl@uaf.edu, 474-7678
Office: 201E Chapman
Hours: 11:15-noon TR, by appointment, or just drop by!

Book cover

Recommended Textbook:
Computer Organization and Design: The Hardware/Software Interface, David Patterson and John Hennessy, Morgan Kaufmann, 3rd Edition.

ADA Compliance: Will work with Office of Disabilities Services (203 WHIT, 474-7043) to provide reasonable accomodation to students with disabilities.

Course Website:


Course Goals and Requirements

By the end of the course, you will be able to understand both the present and future of computer design for performance. Specifically, we will cover instruction-level parallelism, including pipelining, vector processing, SWAR, SIMD, out-of-order execution, and multi-issue; as well as coarser-grained parallelism, including multicore, multi-thread, distributed-memory, and GPU programming. To understand this, you will need to know at least the following topics from the course prerequisites:


Last day to drop: Friday, September 19. Midterm exam: Tuesday, October 21. Last day to withdraw: Friday, October 31. Thanksgiving Break: Thursday, November 20-Sunday, November 23. Last class: Thursday, December 11. Final exam: 8am Tuesday, December 16.

Student Resources

Academic Help: Google, Rasmuson Library, Academic Advising Center (509 Gruening, 474-6396), Math Lab (Chapman Room 305), English Writing Center (801 Gruening Bldg, 478-5246).


Your work will be evaluated on correctness, rationale, and insight, not on successful regurgitation of random trivia. Grades for each assignment and test may be curved up or down if needed. Your grade is then computed based on four categories of work:

  1. HW: Homeworks and machine problems, to be distributed through the semester.

  2. PROJ1: a paper and in-class presentation on an architecture topic of your choice, due in October.

  3. PROJ2: a software development or hardware performance analysis project, due in December.

  4. MT: Midterm Exam, Tuesday, October 21.

  5. FINAL: Final Exam (comprehensive), 8am Tuesday, December 16.

Your overall score is then calculated as:
GRADE = 15% HW + 15% PROJ1 + 15% PROJ2+ 25% MT + 30% FINAL
Letter grades are then assigned at the usual 90/80/70/60 cutoffs.

At my discretion, I may round your grade up if it is near a grading boundary. Homeworks are due at midnight on the day they are due. Late homeworks will receive no credit. At my discretion, I may allow late work without penalty when due to circumstances beyond your control. Projects that are up to two weeks late may be accepted at a 50% grade penalty (e.g., on-time grade: 86%; late grade: 43%). Everything you turn in must be your own work--violations of the UAF Honor code will result in a minimum penalty equal to THAT ENTIRE SECTION OF YOUR GRADE (e.g., one plagiarized homework question will negate an otherwise perfect grade on all homeworks). However, even substantial reuse of other people's work is fine (and not plagiarism) if it is clearly cited; you'll be graded on what you've added to others' work. Group projects (NOT homeworks) are acceptable iff you clearly label who did what work; but I do expect a two-person group project to represent twice as much work as a one-person project. Department policy does not allow tests to be taken early; but in extraordinary circumstances may be taken late.

Course Outline (Tentative)

First section: Make One CPU Faster (1950-2000 AD)

  • History & Trends: Digital Logic, Von Neumann machines

  • Performance Counters, timing, NetRun

  • Physical Reality

    • Photolithography: PCB, semiconductor

    • VHDL, Verilog, netlists

  • Speeding Up Arithmetic

    • MIPS Assembly (for the book)

    • Pipelining, forwarding

    • Dependencies and hazards

    • Branch prediction & speculation

    • Wide issue, Out-of-order

    • Vector processing

    • SWAR, SIMD

  • Speeding Up Memory

    • Cache hardware design, thrashing

    • Cache hit ratio, performance modeling

Second Section: Make More CPUs (2000+ AD)

  • Parallel Hardware / Software

    • SMP, SMT, multicore / threads, tasks, Intel TBB, processes

    • Clusters, MPP / sockets, MPI

    • GPUs, barrel processors, MTA / OpenGL Shading Language

    • FPGAs / VHDL, Verilog