add $18, $19, $20
sw $18, 0($14)
contain a data dependency. The sw instruction cannot access register $18 until the result of the addition is stored in $18. This dependency causes the sw instruction to stall in the Decode stage and results in two holes in the pipeline as shown below:
The holes propagate through the entire pipeline, resulting in two clock cycles where no results are produced. For this pair of instructions, 4 clock cycles are required to complete 2 instructions. The holes introduced by the data dependency reduce the execution speed of the CPU to 50% of the peak MIPS rating.
Instructions which change the PC explicitly are called control instructions. Branch and jump instructions are the primary control instructions. These instructions may change the PC in the Store step of the pipeline.
When a branch condition is not satisfied, the PC is not modified in the Store step. The pipeline will contain various other partially executed instructions which were fetched in sequence following the branch instruction and execution continues without interruption.
When the PC is modified by a branch or jump, the pipeline must be flushed and reloaded with instructions beginning at the new PC. The resulting control dependency introduces 4 holes into a 5 stage pipeline.