Address Modes

MAL instructions consist of an operation code (op-code) and up to 3 operands which are used in performing the specified operation. Since MAL instructions are all 32 bits long, the operand specifications must be smaller than 32 bits.

The manner in which operands are specified is called the address mode. MAL employs three address modes:

Immediate

The operand is contained directly in the instruction. Immediate operands are 16 bits long for all operations except jump instructions, which use 26 bits.

Register

The operand is contained in a register. Register operands are specified by a register number. MAL has 32 general registers which can be specified by 5 bits.

Address

The address of the operand is specified.

MAL load and store instructions all require one register operand and one address. Since an address is 32 bits long, the address cannot be stored directly in the instruction.

MAL employs three techniques to specify operand addresses:

1. Split the 32 bit absolute address into two 16 bit pieces.
2. Add the PC to a shorter relative address stored in the instruction.
3. Store the address in a register.

When a register contains the address for an operand, the operand is specified by enclosing the register name in parentheses. For example, to load the contents of the memory location A into register $8:

        la      $8, A     # load address of A into $8
        lw      $8, ($8)  # load contents of A into $8

performs the same operation as:

        lw      $8, A     # load contents of A into $8

When performing load word and store word instructions, the address in the register must be a word address (multiple of 4 bytes). The byte and half-word load and store operations use register addresses with no restrictions on the address in the register.

Using a register to specify an address allows the manipulation of array elements with computed addresses. For example,

        la      $8, A
        lw      $9, I
        add     $8, $8, $9
        lb      $8, ($8)

will load element A[I] of a byte array into register $8.

The use of register addresses in the store instructions is identical to the load instructions.

The most general form of register addressing in MAL is base displacement or indexed addressing. In this technique, the contents of a register are added to a constant stored in the instruction to obtain the address of the operand. The general load word instruction using base displacement addressing is:

        lw      Rd, I(Rb)

where Rd and Rb are general registers and I is a constant or label. The destination register, Rd, is loaded with the contents of the address formed from the sum of I and the contents of the base register, Rb.

In a base displacement address, either I or (Rb) may be omitted. For example:

        lw      $8, X       # $8 <- contents of address (X)
        lw      $8, ($8)    # $8 <- contents of address in $8
        lw      $8, X($8)   # $8 <- contents of address (X + $8)
        lw      $8, 12($8)  # $8 <- contents of address (12 + $8)

are all variations of base displacement addressing. In the third example above, register $8 would normally correspond to an array element address within the array X. In the last example, register $8 might contain the base address of an integer array whose element [3] is loaded into $8.