SAL vs. MAL

MAL is the MIPS Assembly Language. SAL is an abstraction of MAL. All operations in SAL are performed on variables in memory. This is a memory-to-memory architecture.

The SAL add instruction

        add     A, B, C

fetches the operands B and C from memory, adds them and returns the result to memory location A. The addition operation is performed according to the type of the operands.

MAL is a load/store architecture. In MAL:

1. There are no data types. The bits at a memory location have no inherent meaning and are not self-identifying.
2. Data are moved between RAM and register memory, located in the CPU, using separate load and store instructions.
3. All arithmetic, logical, and conditional branch instructions are performed on register operands only.
4. All instructions use a 32-bit word format.

The SAL add instruction might be represented in machine code as:

Executing this instruction requires the following steps:

1. Fetch instruction (1 clock, 4x32 bit memory access).
2. Update PC (1 clock).
3. Load operands B and C (1 clock, 2x32 bit memory access).
4. Add B and C (1 clock).
5. Store A (1 clock, 1x32 bit memory access).

The total execution time is 5 clock cycles and 7x32 bit memory accesses. Since the access time for RAM is typically 10X the clock cycle time, the CPU spends most of the time waiting for memory access.

For example, a processor with a 150Mhz clock has a cycle time of 6ns. Consumer RAM is available in the 60-80ns range. For a 6ns clock and 60ns RAM, the instruction execution time, T is:

        T = ( 5 x 6ns ) + ( 7 x 60ns ) = 450ns.

The CPU execution time (30ns) accounts for only 6% of the elaspsed time. The CPU is idle 94% of the time.

RISC load/store architectures gain speed and performance by:

1. Separating memory access load/store operations from computational operations. This allows operands to be pre-loaded.
2. Requiring all computational operands to reside in CPU memory (registers) to avoid memory access delays.
3. Making all instructions as short as possible and using a fixed size. This allows instructions to be pre-loaded in blocks to minimize memory access delays in fetching the instructions.