The MIPS architecture, like that of most RISC computers, is difficult to program directly because of its delayed branches and loads and restricted address modes. This difficulty is tolerable since these computers were designed to be programmed in high-level languages and so present an interface designed for compilers, not programmers. A delayed branch takes two cycles to execute. In the second cycle, the instruction immediately following the branch executes. This instruction can perform useful work that normally would have been done before the branch or it can be a nop (no operation). Similarly, delayed loads take two cycles so the instruction immediately following a load cannot use the value from memory.
MIPS wisely chose to hide this complexity by implementing a virtual machine with their assembler. This virtual computer appears to have non-delayed branches and loads and a richer instruction set than the actual hardware. The assembler reorganizes (rearranges) instructions to fill the delay slots. It also simulates the additional, or pseudo, instructions by generating short sequences of actual instructions.
By default, SPIM simulates the richer, virtual machine. It can also
simulate the actual hardware. We will describe the virtual machine
and only mention in passing features that do not belong to the actual
hardware. In doing so, we are following the convention of MIPS
assembly language programmers (and compilers), who routinely take
advantage of the extended machine. Instructions marked with a dagger
( 
) are pseudo instructions.