64-Bit compatability: 64-bit data buses between processor interger unit and instruction and data caches, and between coprocessors and the interger unit.
Out-of-order completion
Different feature sets for different applications: THUMB, VFP, Jazelle
The Pipeline
Uses pipeline forwarding
Scalar initially, changes to parallel pipelines after decoding
ALU/MAC/LS - Arithmatic Logic Unit/Multiplier Accumulator/Load and Store
Out-of-order exec and parallel pipelines
Predictive Branching
What is it?
64-entry, 4 state branch target address cache (BTAC)
Stages: Strongly Taken/Weakly Taken/Strongly not Taken/Weakly not Taken
Folding branchs
~85% of branches are correctly predicted, resulting in saving five clock cycles for every correct prediction